Wish List - Hardware:FPGA - Revision history

Basseuph at 20:28, 18 July 2008

2008-07-18T20:28:03Z

Jcarroll: /* AT91CAP9S500A (ARM9 + FPGA-port) */

2008-07-15T20:13:19Z

‎AT91CAP9S500A (ARM9 + FPGA-port)

Glenn: +info

2008-02-15T10:57:51Z

+info

Glenn: +link "...fully open graphics card..."

2007-12-22T16:36:19Z

+link "...fully open graphics card..."

Glenn: +Category:Hardware ideas

2007-10-23T20:57:16Z

+Category:Hardware ideas

Glenn: +link

2007-10-23T19:49:48Z

+link

Glenn: +sources

2007-10-23T19:48:41Z

+sources

Speedevil: paste

2007-10-15T15:42:33Z

paste

Speedevil: add

2007-10-15T15:41:08Z

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New page

===AT91CAP9S500A (ARM9 + FPGA-port)===
Why FPGA?:
*[http://hardware.silicon.com/servers/0,39024647,39166443,00.htm?r=1 20 March 2007 Green supercomputer is 'go' in Scotland] Quote: "...A supercomputer 10 times more energy efficient and up to 300 times faster than its traditional equivalents..."

Take a look at this microcontroller, that integrates an ARM9 microcontroller and a dedicated FPGA port: AT91CAP9S500A. It has "only" a max. clock at 200MHz, but can use a FPGA for hardware acceleration, that could be used for video (de)compression, [http://en.wikipedia.org/wiki/AacPlus_v2 aacPlus v2]/[http://en.wikipedia.org/wiki/HE-AAC_v2 HE-AAC v2] sound (de)compression and many other things. HE-AAC v2 is better than [http://en.wikipedia.org/wiki/MP3 MP3].
*[http://www.atmel.com/dyn/products/product_card.asp?family_id=689&family_name=AT91CAP+Microcontrollers&part_id=4137 AT91CAP9S500A] Quote: "...The AT91CAP9S500A is built around a 12-layer bus matrix, allowing a maximum internal bandwidth of twelve 32-bit buses. Its distributed DMA architecture enables multiple data transfers to take place between the processor, memories and peripherals with minimal processor overhead...".
*[http://www.atmel.com/dyn/resources/prod_documents/doc6310.pdf GNU-Based Software Development on AT91SAM Microcontrollers]
*Maybe this is a good tool?: [http://www.jhdl.org/ BYU JHDL, Open Source FPGA CAD Tools]
*[http://www.eetimes.com/showArticle.jhtml;?articleID=197002705 02/05/2007, FPGA tool bottleneck stalls HPC] Quote: "...Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers simply trying to accelerate an algorithm..."

This seems to be a good hardware mix (ARM+FPGA). It does [http://en.wikipedia.org/wiki/Theora Ogg Theora] or [http://en.wikipedia.org/wiki/MJPEG MJPEG] in the FPGA with 1 million gates:
*http://sourceforge.net/projects/elphel, [http://wiki.elphel.com/index.php?title=10353 board 10353], [http://wiki.elphel.com/index.php?title=Camera_hardware camera hardware], [http://wiki.elphel.com/index.php?title=Main_Page Main page], [http://www.elphel.com/articles/index.html Imaging solutions with Free software and open hardware]

Just another FPGA+microcontroller example:
*[http://melzer.ch/html/body_alya.html The Alya Project] ([http://home.nikocity.de/andymon/hfg/Alya/alya.html old page])
*[http://melzer.ch/ALYA.ASM PIC assembler source code], [http://melzer.ch/ALYA.TDF Altera FPGA code]. Schematic: [http://melzer.ch/Schaltplan1.gif], [http://melzer.ch/Schaltplan2.gif], [http://melzer.ch/Schaltplan3.gif]

I do not think this means what you think it means... I read "...and a metal programmable (MP) block of 500K gates of digital logic." as meaning that it's a one-time programmable block, more akin to a standard-cell ASIC than an FPGA. This is supported by the fact that their development board contains a separate FPGA chip. Now, granted, having a 500K gate ASIC on board an ARM is a cool thing... but not quite as cool as this chip appeared at first glance.

@@ Line 29: / Line 29: @@
 **XC3S1400AN-4FGG676CES $91
 **XC3S200AN-4FTG256CES $25.87
 ====Tool for FPGAs====

@@ Line 12: / Line 12: @@
 **[http://www.arsc.edu/news/archive/fpga/Wed-1030-Najjar.pdf Compiled Acceleration of C Codes for FPGAs (pdf)] Quote: "...Riverside Optimizing Compiler for Configurable Computing. A C/C++ to VHDL compiler...Same speed as hand-written VHDL codes...[http://www.cs.ucr.edu/~roccc/ ROCCC] is not intended to compile the whole code to FPGA. Only compute intensive code segments, typically parallel loops..."
 **[http://www.jhdl.org/ BYU JHDL, Open Source FPGA CAD Tools]
 *[http://www.eetimes.com/showArticle.jhtml;?articleID=197002705 02/05/2007, FPGA tool bottleneck stalls HPC] Quote: "...Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers simply trying to accelerate an algorithm..."

← Older revision		Revision as of 20:57, 23 October 2007
Line 35:		Line 35:
	**[http://vlsi.cornell.edu/fpga.php Asynchronous VLSI and Architecture, Cornell University: Asynchronous Field-Programmable Gate Arrays (AFPGAs)] Quote: "...integrated pipelining support..."		**[http://vlsi.cornell.edu/fpga.php Asynchronous VLSI and Architecture, Cornell University: Asynchronous Field-Programmable Gate Arrays (AFPGAs)] Quote: "...integrated pipelining support..."
	**[http://citeseer.ist.psu.edu/teifel03programmable.html Programmable Asynchronous Pipeline Arrays (2003) John Teifel, Rajit Manohar]		**[http://citeseer.ist.psu.edu/teifel03programmable.html Programmable Asynchronous Pipeline Arrays (2003) John Teifel, Rajit Manohar]
		+
		+	[[Category:Hardware ideas]]

@@ Line 8: / Line 8: @@
 *[http://www.atmel.com/dyn/resources/prod_documents/doc6310.pdf GNU-Based Software Development on AT91SAM Microcontrollers]
 *Maybe this is a good tool?:
-**[http://www.arsc.edu/news/archive/fpga/Wed-1030-Najjar.pdf Compiled Acceleration of C Codes for FPGAs (pdf)] Quote: "...Riverside Optimizing Compiler for Configurable Computing. A C/C++ to VHDL compiler...Same speed as hand-written VHDL codes...ROCCC is not intended to compile the whole code to FPGA. Only compute intensive code segments, typically parallel loops..."
+**[http://www.arsc.edu/news/archive/fpga/Wed-1030-Najjar.pdf Compiled Acceleration of C Codes for FPGAs (pdf)] Quote: "...Riverside Optimizing Compiler for Configurable Computing. A C/C++ to VHDL compiler...Same speed as hand-written VHDL codes...[http://www.cs.ucr.edu/~roccc/ ROCCC] is not intended to compile the whole code to FPGA. Only compute intensive code segments, typically parallel loops..."
 **[http://www.jhdl.org/ BYU JHDL, Open Source FPGA CAD Tools]
 *[http://www.eetimes.com/showArticle.jhtml;?articleID=197002705 02/05/2007, FPGA tool bottleneck stalls HPC] Quote: "...Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers simply trying to accelerate an algorithm..."

← Older revision		Revision as of 15:42, 15 October 2007
Line 17:		Line 17:

	I do not think this means what you think it means... I read "...and a metal programmable (MP) block of 500K gates of digital logic." as meaning that it's a one-time programmable block, more akin to a standard-cell ASIC than an FPGA. This is supported by the fact that their development board contains a separate FPGA chip. Now, granted, having a 500K gate ASIC on board an ARM is a cool thing... but not quite as cool as this chip appeared at first glance.		I do not think this means what you think it means... I read "...and a metal programmable (MP) block of 500K gates of digital logic." as meaning that it's a one-time programmable block, more akin to a standard-cell ASIC than an FPGA. This is supported by the fact that their development board contains a separate FPGA chip. Now, granted, having a 500K gate ASIC on board an ARM is a cool thing... but not quite as cool as this chip appeared at first glance.
		+
		+	==Possible FPGA==
		+	This FPGA is just an example:
		+	*[http://www.xilinx.com/products/silicon_solutions/fpgas/spartan_series/spartan3an_fpgas/capabilities/index.htm Spartan-3AN FPGA Capabilities] Quote: "...Simple and secure embedded application storage with up to 11Mb of integrated user Flash...Enable simple arithmetic and math functions as well as advanced DSP functions to derive over 330 Giga MACs/sec...Up to 32 18 x 18 embedded multipliers support 18-bit signed or 17-bit unsigned multiplication, and can be cascaded to support wider bits..."
		+	**XC3S1400AN-4FGG676CES $91
		+	**XC3S200AN-4FTG256CES $25.87
		+
		+	====Tool for FPGAs====
		+	*[http://www.xilinx.com/ise/logic_design_prod/webpack.htm xilinx.com: ISE WebPACK is the industry´s only FREE, fully featured front-to-back FPGA design solution for Linux, Windows XP, and Windows Vista]
		+
		+	===Asynchronous FPGA, AFPGA===
		+	*[http://www.achronix.com/products.html Achronix-ULTRA]
		+	**[http://www.pldesignline.com/news/186700955 Achronix preps 2-GHz Asynchronous FPGA for sampling in 2007]
		+	**[http://vlsi.cornell.edu/fpga.php Asynchronous VLSI and Architecture, Cornell University: Asynchronous Field-Programmable Gate Arrays (AFPGAs)] Quote: "...integrated pipelining support..."
		+	**[http://citeseer.ist.psu.edu/teifel03programmable.html Programmable Asynchronous Pipeline Arrays (2003) John Teifel, Rajit Manohar]

@@ Line 4: / Line 4: @@
 *[http://hardware.silicon.com/servers/0,39024647,39166443,00.htm?r=1  20 March 2007 Green supercomputer is 'go' in Scotland] Quote: "...A supercomputer 10 times more energy efficient and up to 300 times faster than its traditional equivalents..."
 *[http://wiki.duskglow.com/tiki-index.php?page=OGPN17 Dec 10th 2006 Open Graphics Project Newsletter] Quote: "...We know how long you have dreamt about the possibility of a fully open graphics card. We have the First Photographs of what will be a genuinely Open Graphics Card. This card is not a dream. The card is real...The prototype, is a PCI based FPGA development card with dual DVI output, TV-out and three 300MHz Analog to Digital Converters..."
 Take a look at this microcontroller, that integrates an ARM9 microcontroller and a dedicated FPGA port: AT91CAP9S500A. It has "only" a max. clock at 200MHz, but can use a FPGA for hardware acceleration, that could be used for video (de)compression, [http://en.wikipedia.org/wiki/AacPlus_v2 aacPlus v2]/[http://en.wikipedia.org/wiki/HE-AAC_v2 HE-AAC v2] sound (de)compression and many other things. HE-AAC v2 is better than [http://en.wikipedia.org/wiki/MP3 MP3].

@@ Line 1: / Line 1: @@
 ===AT91CAP9S500A (ARM9 + FPGA-port)===
 Why FPGA?:
 *[http://hardware.silicon.com/servers/0,39024647,39166443,00.htm?r=1  20 March 2007 Green supercomputer is 'go' in Scotland] Quote: "...A supercomputer 10 times more energy efficient and up to 300 times faster than its traditional equivalents..."
@@ Line 6: / Line 7: @@
 *[http://www.atmel.com/dyn/products/product_card.asp?family_id=689&family_name=AT91CAP+Microcontrollers&part_id=4137 AT91CAP9S500A] Quote: "...The AT91CAP9S500A is built around a 12-layer bus matrix, allowing a maximum internal bandwidth of twelve 32-bit buses. Its distributed DMA architecture enables multiple data transfers to take place between the processor, memories and peripherals with minimal processor overhead...".
 *[http://www.atmel.com/dyn/resources/prod_documents/doc6310.pdf GNU-Based Software Development on AT91SAM Microcontrollers]
-*Maybe this is a good tool?: [http://www.jhdl.org/ BYU JHDL, Open Source FPGA CAD Tools]
+*Maybe this is a good tool?:
 *[http://www.eetimes.com/showArticle.jhtml;?articleID=197002705 02/05/2007, FPGA tool bottleneck stalls HPC] Quote: "...Current FPGA synthesis, placement and routing tools are written for hardware designers, not software programmers simply trying to accelerate an algorithm..."