User:Mmontour/HHNotes

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* After performing the above reads (two dumps of all register values), any channel 0 register can be re-written (0xFE command) with its current value, and this will not change the value of any other registers in the  device. Note - this applies if there is a 0.5s delay after the 0xFE, before the next 0xFF. With no delay, some changes are observed when writing register 1 (and others) and the device may return invalid packets.
 
* After performing the above reads (two dumps of all register values), any channel 0 register can be re-written (0xFE command) with its current value, and this will not change the value of any other registers in the  device. Note - this applies if there is a 0.5s delay after the 0xFE, before the next 0xFF. With no delay, some changes are observed when writing register 1 (and others) and the device may return invalid packets.
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* Channel 0 register 08: Bit 0x0004 (counter reset) stays set if it's turned on with the counter stopped. It is automatically cleared once the counter is started (bit 0x2000).

Revision as of 08:55, 20 August 2007

This page contains some of my notes about the Hammerhead GPS protocol.

Based on my observations as well as other people's comments (including the "sphyrna" documentation), I treat the "0xFF" packet as a request to read registers from the device. These registers are potentially addressed from 0x00 to 0xFF (the 5th byte of the packet) and are specific to each "channel" (0x00 to 0x08, the lower 4 bits of the 4th byte of the packet). I will use this terminology on this page.

  • It looks like the last byte of a packet from the GPS may be 0x00 rather than 0xFC in some error conditions. This is not confirmed and may just be a bug in my software, but I saw this when I was sending data to the device too quickly (before receiving its full response).
  • The first time after the device is powered up, reading registers 0x22 and 0x23 on channels 1-8 returns a value of 0. On subsequent reads, these registers return values of 0x00000005 and 0x80000000 respectively (note - may be endian-flipped).
  • After performing the above reads (two dumps of all register values), any channel 0 register can be re-written (0xFE command) with its current value, and this will not change the value of any other registers in the device. Note - this applies if there is a 0.5s delay after the 0xFE, before the next 0xFF. With no delay, some changes are observed when writing register 1 (and others) and the device may return invalid packets.
  • Channel 0 register 08: Bit 0x0004 (counter reset) stays set if it's turned on with the counter stopped. It is automatically cleared once the counter is started (bit 0x2000).
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This page contains some of my notes about the Hammerhead GPS protocol.

Based on my observations as well as other people's comments (including the "sphyrna" documentation), I treat the "0xFF" packet as a request to read registers from the device. These registers are potentially addressed from 0x00 to 0xFF (the 5th byte of the packet) and are specific to each "channel" (0x00 to 0x08, the lower 4 bits of the 4th byte of the packet). I will use this terminology on this page.

  • It looks like the last byte of a packet from the GPS may be 0x00 rather than 0xFC in some error conditions. This is not confirmed and may just be a bug in my software, but I saw this when I was sending data to the device too quickly (before receiving its full response).
  • The first time after the device is powered up, reading registers 0x22 and 0x23 on channels 1-8 returns a value of 0. On subsequent reads, these registers return values of 0x00000005 and 0x80000000 respectively (note - may be endian-flipped).
  • After performing the above reads (two dumps of all register values), any channel 0 register can be re-written (0xFE command) with its current value, and this will not change the value of any other registers in the device. Note - this applies if there is a 0.5s delay after the 0xFE, before the next 0xFF. With no delay, some changes are observed when writing register 1 (and others) and the device may return invalid packets.
  • Channel 0 register 08: Bit 0x0004 (counter reset) stays set if it's turned on with the counter stopped. It is automatically cleared once the counter is started (bit 0x2000).