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Return to Neo 1973 GTA01 Power Management.

Personal tools
In progress: This article or section documents one or more features whose implementation are in progress.

This page details the power managment of the Phase 1 Neo1973. Much of it is inapplicable to earlier models.

Power management is of utmost concern to any mobile device. Battery power is quite limited, so we need to make sure we try our best to conserve it.

This is very much partially implemented at the moment.

Required kernel mode power saving, and relative saving of battery life.
Option Note Average saving over next lowest
power state the description
is the total effect on battery life
External peripheral control Ability to dim backlight, turn on and off GSM, GPS, and other devices outside the CPU Huge (700mW) Implemented
Slow Mode The CPU clock is 12MHz, this is the lowest power mode with the CPU awake Huge(300mW) Not implemented
Variable CPU core voltage Dynamically alter CPU core voltage according to frequency Large(50mW) Not implemented
CPU Idle mode Turn off CPU clock while rest of SoC remains awake Moderate(150mW) Not implemented
Variable CPU frequency ~20Mhz to 266Mhz Vary CPU frequency to lower power consumption. Huge(250mW) Not implemented
Tickless Kernel Remove periodic timer interrupts in kernel Modest(10mW?) Not implemented
Rapid Suspend-RAM Suspend CPU totally and resume when required in under 1s. Huge (50mW) Not implemented

Required user-mode power saving
Option Note Saving Status
General speed optimisation of all software With variable CPU clock, the less CPU needed, the less power. Moderate (Large with backlight off) In Progress
Smart turning off unused peripherals Interacting with kernel mode drivers to turn off bits the user isn't using Large
Seamlessly switching to 256 colour The LCD controller supports pallete mode. This would reduce memory bus traffic by a third. Small Of debatable value - only for P1 (?)

This page tries to describe the various power management features of the Neo1973 Hardware, their states, transitions, etc. First, we start by describing the power states of the individual hardware components. Then we look at it from a System Integration point of view.

S3C2410 SoC

The S3C2410 SoC section is an overview of the S3C2410 power states or modes and their capabilities. The S3C2410 has the following modes:

Power states for the S3C2410 SoC(CPU) including approx memory bus current
Mode Frequency Power consumption Wakeup sources Note
Normal Mode 33-266Mhz (around 50-335mW depending on speed) Awake
Idle Mode 33-266Mhz around 50-170mW depending on speed Any interrupt FCLK disconnected
Slow Mode 12Mhz 40mW Awake, can vary clock speed as desired on interrupts. CPU clock (FCLK), SDRAM, bus clocks set by 12Mhz crystal.
Power_off Mode off .2mW (@2V) GSM, buttons, touchscreen, charger/USB connect, low battery EINT[0...15], RTC Alarm Interrupt, nBATT_FAULT pin. SDRAM self-refresh, RTC powered.
Peripheral Power Note constraints
USB-H 1mW The USB host driver
USB-D 6mW The USB device driver PCLK>20Mhz
LCD driver 20(qvga)-80mW LCD driver HCLK>VCLK*4 (p386) VCLK(vga)=19Mhz VCLK(qvga)=4.75Mhz = CPU clock 80Mhz min(seems to work at 50Mhz according to u-boot pll set) or 32Mhz (min variable CPU speed)
PLL ?mW Phase locked loop, needed if not in slow mode.
Serial 7mW 2/3 integrated serial ports

System design considerations

In order to fully support Power_off mode, we need to

  • Be able to switch off VDDi/VDDiarm/VDDi_MPLL/VDDi_UPLL separately from VDDalive

PCF50606 PMU

This is an overview of the PCF50606 power modes / state transitions


Condition: Vbat < Vverylowbat && Vback < Vlowback && Vchgvin < Vlowchg

Human-Readable: If main battery voltage < 2.7V and backup battery voltage < 1.3V and charger voltage < 2.7V


Condition: Vbat < Vverylowbat && (Vback > Vlowback || Vchgvin > Vlowchg)

Human-readable: If main battery voltage < 2.7V and at least backup battery voltage > 1.3V or charger voltage > 2.7V.


Condition: Vbat > Vverylowbat

Human-readable: If main battery voltage > 2.7V


Condition: Vbat > Vlowbat Human-Readable: If main battery voltage > 2.8V (configurable up to 3.4V) Transition from STANDBY to ACTIVE: If ONKEY button is pressed, or RTC Alarm, or EXTON or charger insert or pen-down by touchscreen (we don't use the PMU TS controller)


Deep Standby

In this mode, only the supply power is activated


Holds register data with clock stopped


Fully powered up and operational

System Level

This is a description of the system-level power management.

System Power states

In order to do system-level power managment, we need to introduce state definitions with their according state names. The state names are prefixed by SYS_POWER_.

System power managment states. Name prefixed with SYS_POWER_ PMU off is turned off by switching off the requisite output of the PCF50606
Name Note PCF50606
PSU chip
LCD driver
GSM GPS Bluetooth Backlight
NO No main battery or USB charger. Backup battery operational Save Off PMU off Off - no Vbatt PMU off PMU off off
OFF "Switched Off" - no functionality Standby PMU off PMU off Off by MODEM_ON to LOW PMU off PMU off off
SLEEP Suspend-RAM (in pocket waiting for a call) Active Power_Off PMU Off On by MODEM_ON to HIGH Optional Deep Standby Off
SCRSAVE Screen Saver Active SLOW, IDLE SLEEP On by MODEM_ON to HIGH Optional Optional Off
ON Normal active state Active On Normal On by MODEM_ON to HIGH Optional On On, PWM'd brightness

Wake-up reasons

In the following events, we want the main CPU to be able to be woken up from Power_off (SYS_POWER_SLEEP) state:

Events from GSM

  • Incoming phone call
  • Incoming SMS
  • Loss of network signal

The GSM daemon configures the GSM Modem so as to wake the CPU when events happen.

The S3C2410 has the EINT0 pin of the S3C2410 connected to the GSM modem, which wakes it on configured events.

GPIO from Bluetooth

PIO_2 of the DFBM-CS320 is connected to GPC7 of the s3c2410.
PIO_5 of the DFBM-CS320 is connected to GPC5 of the s3c2410.
BT_EN of the DFBM-CS320 is connected to GPB5 if the s3c2410. [1]

Button Press

If somebody pushes either the Neo1973 Aux Button or the Neo1973 Power Button, the system shall wake up.

Power Button

During suspend, the PMU is configured to allow PWRONF events to generate interrupts to the CPU. (This is if PWR_IRQ is the internal signal from the PMU, mentioned in gpio.txt)

Aux Button

The Aux button is connected the EINT6 pin, which can wake-up the CPU from Power_off.

This means that resuming on Aux button will work out-of-the-box

Charger Events

If a charger plug (or any other USB device) is connected, the device shall resume and update the battery [charger] status. Also, charger errors such as over/undervoltage, over/under-temperature shall be reported.


During suspend, the PMU is configured to allow EXTONR,CHGERR and related events to generate interrupts to the CPU.

In GTA01Bv4, the PMU IRQ is connected to EINT9.

NOTE: Up to GTA01Bv3, the PMU IRQ is connected to EINT16, i.e. an interrupt source that cannot wake-up from Power_off mode!


NOTE: This section reflects the wiring of power rails in GTA01Bv04


  • Battery terminal voltage
  • Used by
    • LM4857 Amplifier (vdd1-4)
    • PCF50606 PMU
    • LCM Backlight (via U6001)
    • U7602 AVDD/GL_3V3 regulator
    • GSM Modem


  • This is the S3C2410 Core Voltage
  • Generated by PMU DCUD
  • Used by
    • S3C2410 (vddiarm/vddi/vddi_mpll/vddi_upll)


  • Standby Voltage for S3C2410
  • Generated by PMU D3REG
  • Used by
    • S3C2410 (vddalive/rtc)


  • Generated by PMU DCDE
  • Used by
    • lots of pullups
    • U1502 (latch for GSM UART)
    • S3C2410 VDDMOP
    • S3C2410 VDDOP
    • S3C2410 VDDA_ADC
    • S3C2410 nBATT_FLT
    • S3C2410 !EXTCLK
    • SDRAM_VCC3
    • FLASH_3V3
    • LM4857 Amplifier (i2cvdd)
    • Vibrator
    • Touch panel transistors
    • SD_3V3 via U7501
    • PMU (avdd)


  • Generated by PMU DCDF
  • Used by
    • AGPS (vdd_core)


  • Generated by PMU D2REG
  • Used by
    • AGPS (vdd_pllreg)


  • Generated by U7602
  • Used by
    • AGPS (vdd_io/vdd_lpreg)
    • AGPS (X7601 -> rtcclk)
  • Controlled by



  • Generated by U7602
  • Used by
    • AGPS (lna power int/ext, antenna switch)
  • Controlled by


  • Generated by PMU IOVDD
  • Used for
    • Audio Codec (digital and analog)


  • Generated by PMU D1REG
  • Used by
    • Bluetooth Module


  • Generated by PMU LPVDDD
  • Used by
    • Headset/GSM Uart Latch
    • LCM


  • Derived from IO_3V3
  • Used by
    • NAND Flash


  • Derived from IO_3V3
  • Used by
    • SDRAM


  • Generated by U7501
  • Used by
    • microSD slot
  • Controlled by
    • SD_ON GPIO

Kernel API

Userspace API

Approximate power draw of various subsystems

In P0 and P1 phones, the battery has a total of 1200mAh, at 3.6V. This is approximately 3500mWh, once power supply losses are taken into account. The figues below are estimates from datasheets.

These do not take into account the severe hardware bugs of phase 0 hardware, which severely affect power use.

  • LCD
    • 500mW with backlight at full brightness
    • 50mW with backlight at 10%
      • Based on rough measurements of P0 hardware.
  • CPU
    • 320mW @ 200MHz
    • 450mW @ 266MHz
    • 140mW @ 200MHz idle.
    • 50mW @ 12MHz (slow mode)
      • These include fudge factors for RAM and other systems, from the CPU datasheet.
  • RAM 600mW at 600Mbytes/sec, power use broadly proportional to transfer rate.
  • Bluetooth
    • 63mW @ Tx Burst (file transfer, send)
    • 36mW @ Rx Burst (file transfer, receive)
    • 3.6mW @ Idle, beacon only
      • Based on the datasheets provided
  • GSM ?
    • Idle, but connected to network, probably 30mW (based on similar devices)
    • Active on a call - up to 500mW or so, perhaps considerably less if close to a tower.
      • Based on 2W radio on 1/8th of the time as it is in a full rate codec.
  • GPS
    • 45mW
      • Based on comparison with a broadly similar (though not as fully featured chip from Maxim
CPU clock speed constraints
Frequency(Mhz) Notes QVGA LCD VGA LCD USB device
12 Slow mode No No No
12-33.74 Impossible or violates PLL spec
33.75-67.5 Yes No Yes (with proper setting of HCLK divider)
79-266 Yes Yes Yes
268-300 Overclocking ? ? ?

Recommended clock speeds: 12 33.75 45 48 50.7 56.25 67.5 79 84.75 90 101.25 113.0 118.5 124.0 135.0 147.0 152 158 170 180 186 192 202.8 266 268 270

Other clock speeds are possible (in the 33.75-266Mhz range) by setting the PLL, however, the datasheet strongly recommends these, and recommends contacting samsung for speeds not listed above.

This would imply that with the CPU constantly on in low power mode, GPS and GSM blipping on and off, and display off, the worst case power consumption is probably around 70mW, leading to a battery life of 2 days. If the CPU is turned off, battery life rises significantly.

With everything on, playing video with sound, for example should get well over 3 hours. (500mW LCD + 320mW CPU + 200mW audio + 50mW GPS. 4.5Wh at 1.1W draw)

Both voltage and clock speed to the CPU core can be altered. Exactly how this will work with the hardware is yet to be determined. It is possible that it may be capable of playing MP3s with the CPU clock at 60Mhz. This would considerably extend battery to well over 10 hours. Optimistically >24 hours of mp3.

Measured power draw on phase 0 neo1973

I played with old ampermeter, old nokia 3110 (as a powersupply) and phase0 neo1973 a bit. It appears to eat 1.02 mW while powered off, 1.02W while booted (backlight on), ~0.51W while sleeping (with backlight on) and 1.4W while loading applications.